DSM-Directed Chip Design and Verification

DSM 2010: Proceedings of the 12th International DSM Conference, Cambridge, UK, 22.-23.07.2010

Year: 2010
Editor: Wynn, D.C.; Kreimeyer, M.; Eben, K.; Maurer, M.; Lindemann, U.; Clarkson, P.J.
Author: Minogue, P.
Section: Industry Applications
Page(s): 447-460


The current approach to integrated circuit (I.C.), or chip, design is not always optimum in terms of “Design-for-Layout”. Ideally, it is good practice to create the design schematics and layout so that a one-to-one correspondence exists at all levels of the schematic/layout hierarchy. Instead, the current approach can be somewhat adhoc and therefore prone to non-optimum schematic/layout hierarchy creation, resulting in inefficient development execution. In addition, the current approach is limited in that it typically does not try to systematically optimise the project (sub-)team members’ participation in terms of sub-block interface design and verification. This can result in simulation blindspots or omissions. We can use the Design Structure Matrix (DSM) and Domain Mapping Matrices (DMM), in a Multi Domain Mapping (MDM) methodology, to (i) ensure optimised schematic/layout hierarchy creation and (ii) determine a more optimum configuration of (sub-)team members and design/verification tasks, in a visually powerful way. DSM-directed chip design and verification should be more efficient and of higher quality, as a consequence.
The DSM has been applied to chip development in the past in the context of activity- or task-based DSMs, using sequencing techniques. The application suggested here involves component- and team-based DSMs, using clustering techniques.

Keywords: integrated Circuit, Design, Verification, DSM, DMM, MDM, Virtual Clustering, Degree of Diagonality


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